1. Field of the Invention
This invention relates in general to a chip package that utilizes both BGA and QFP lead types, and more particularly to a process and assembly for a hybrid chip package that can accommodate the temperature changes of a high-speed device and how they translate to the package materials and associated printed circuit board.
2. Description of the Related Art
In response to current demands from the electronics industry to produce smaller, faster, and more reliable devices, many semiconductor manufacturers have looked at exploiting the advantages of ball grid array ("BGA") technology. There are three major types of BGA assemblies in use today primarily differentiated by the substrate type: tape ball grid array ("TBGA"), plastic or laminate ball grid array ("PBGA") and ceramic ball grid array ("CBGA").
FIGS. 1A and 1B show a cross-sectional and a top plan view of a conventional high-speed BGA package 9A before being attached to a printed circuit board ("PCB"). More specifically, these figures show a BGA substrate 15 having contact wires 17 and a solder bump structure 19. Contact wires 17 mount between the chip contact terminals 11A and the substrate contact terminals 15A. The solder bump structure 19 includes an array of solder bumps 19A and pads 19B attached to the bottom surface of the substrate 15 to establish a connection with the contact wires 17 and chip 11 through the substrate 15. A protective layer 13, of a material such as an epoxy resin, is deposited to encapsulate the chip 11, the contact wires 17, and a portion of the substrate 15.
Once the above package is attached to a PCB 20 by a known method (see FIG. 2), the chip can be activated. During operation, the chip 11 will cycle through high and low temperatures which will in turn strain the resultant structure near a peripheral region 21 where the solder balls 19A contact the PCB contacts. This strain is due to different coefficient of thermal expansion ("CTE") properties of the assembly. More specifically, the PCB 20 provides a greater CTE change S1 during operation than the CTE change S2 provided by the package. These strains induce the BGA joints to flake 19C and crack 19D as illustrated in FIG. 2.
Currently, the chip package of choice for high-speed or signal integrity is the ceramic flip chip, such as an SRAM chip package on a 1 inch ceramic substrate having a ball grid array ("BGA") structure containing up to 300 solder balls with a pitch of about 1.27 mm. This chip reaches operational temperatures between about 27 and 110 degrees Celsius. Unfortunately, as mentioned above this type of chip package has a tendency to fail during operation because of its excessive thermal cycling properties. More specifically, the differences in the CTE between the ceramic package and the fiberglass/resin PCB assembly causes excessive strain on the BGA pins at the edges of the chip during operational cycles. Consequently, the BGA joints flake or crack to form electrical opens making the package unreliable and ineffective.
The magnitude of the operational strain on the BGA pins depends on the geometry of the chip, the temperature difference and the CTE's of the materials involved.
The operating temperature of a given chip depends on its function, signal speed and technology. As performance increases and chip size decreases, temperatures tend to follow. It is very difficult to keep chips operating at a low temperature. The materials can be changed at a price. Exotic board materials with smaller CTE's (closer to ceramics) are available. However, they do not have the track record of success that conventional FR4 board materials. In turn, their electrical properties are so different, that board designs have to be adjusted for them. Given the current focus on keeping costs low, this is an unattractive option.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.